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Sat 04 of Feb, 2012 (18:27 UTC)

V6Z80P Documentation

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ROM and Bootcode

Created by: phil, Last modification: Sun 02 of Jan, 2011 (17:36 UTC)

OSCA ROM Operations (v6.14 in OSCA661+):


In OSCA the Z80 starts up from a 512 byte blockram in the FPGA (mapped into $0-$1ff). This ROM code tells the PIC microcontroller to clock out 3520 bytes from the SPI EEPROM (EEPROM location $0F000 onwards) - this is the Bootcode. The Z80 writes the data from the EEPROM to system memory $200 onwards, checks the CRC checksum (last two bytes) and executes it (JP $200) if all OK. If CRC doesn't match, the display flashed magenta and the EEPROM databurst is requested again, this time from EEPROM location $1F000. If this also fails the ROM waits for the bootcode via serial link (display turns grey). It is possible to force the serial download from the outset by holding UP+RIGHT+FIRE on joystick in port A upon power up/reset.

Bootcode operations (v6.13)


The bootcode resets the keyboard, shows welcome text (white on black background) and looks for an Operating System. First it checks the root dir of any attached SD card for an .OSF file, next it looks at $00800 in the onboard EEPROM, finally it requests a serial download. The OS code is loaded to $1000 and executes from $1010. To skip the SD card and EEPROM check and immediately go to serial download, press the ESC key on boot. To reboot whilst the waiting for a serial download, press Left CTRL (the serial download also times out and reboots after 1 minute of inactivity). During the boot process it is possible to press F1-F7 to force FPGA reconfiguration from the respective slot.


To permanently change the ROM at $000-$1FF:


As it is internal to the FPGA, the ROM binary is part of the OSCA configuration file. It has to be converted to an ASCII format which can be inserted into the Xilinx project's constraints (.ucf) file. (Use the PC util "ROM_to_fpga_constraints.exe" for this). Once pasted over the old ROM section of the .ucf file in the Xilinx project, the project needs to be recompiled using Xilinx Webpack 10.1 and the output (.bin) file reprogrammed into a config slot in the EEPROM (using the EEPROM.EXE program or an external programming unit).

(For applications requiring access to memory locations $0-$1ff OSCA allows the ROM to be paged out and replaced by system RAM.)

To change the bootcode:


Assemble the bootcode and use the PC based "Bootcode_CRC.exe" util to output a file with the correct CRC. You can then write this to the EEPROM with the EEPROM.EXE tool.


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