Normal power On activity

1. Power switched on.
2. Z80 CPU is held reset (by FPGA "done" line)
3. PIC checks JTAG-mode jumpers (J1 and J2)
   If jumpers are installed, the yellow LED flashes rapidly until the FPGA has been manually configured by downloading a .bit file from Xilinx impact software on PC.
4. If the JTAG-mode jumpers are not installed, the PIC sends the config data stored on the from EEPROM to the FPGA (the address from which this config data is sourced can be changed via software, by default the source address is $20000)
5. If the FPGA starts up correctly with the architecture file supplied (ie: the FPGA "Done" line goes high) the yellow LED stays on. If the config fails, the yellow LED will pulse and the PIC goes back to step 2.

1. The Z80 is released from reset and runs the ROM code which is held internally in the FPGA (mapped into $0-$1ff). This short bootstrap ROM sends a request for a "Bootcode" file to the PIC (from EEPROM address $0F000, loaded to Z80 address $200-$FBF)
2. If the bootcode is received OK it executes; Keyboard resets, welcome text appears etc. If no bootcode is received, or the CRC word at offset $DBE does not match that computed from the rest of the file; the display flashes: magenta=CRC error, yellow=timed out. At this point, EEPROM location $1F000 will be checked for the bootcode.
3. Once loaded, the Bootcode looks for an OS on the SD card, if not found it looks at EEPROM memory location $800. (If at this time the ESC key is pressed, the bootcode prompts for code to be serially downloaded instead. If keys F1-F3 are pressed, the FPGA reconfigures from the relevent slot.) If an OS file is found, it is loaded to $1000, the checksum is tested and if OK, code executes from $1010.
4. If no OS is found then the bootcode requests a serial download. Files downloaded at boot time are loaded to $1000 and code execution starts at $1010.