Config Problems

If the FPGA does not receive a valid configuration pattern from the EEPROM upon power on, the yellow LED will flash slowly (around 1 flash per second). There are various ways to fix this..

Original V6Z80P Board

OPTION 1: With Config PIC firmware v616+ the Active Slot can be changed manually. Assuming there is a working config in Slot 1, 2 or 3 and the problem is just that the Active Slot selection is pointing at a bad config:

• Power off.
• Install jumper J2 only
• Power on (yellow led flashes rapidly - JTAG mode).
• Remove jumper J2
• The PIC will reset the active slot to 1 (indicated by 1 pulse of the red LED) The yellow led lights up for 4 seconds then Slot 2 is set (2 flashes of red LED), again there's a 4 second pause, finally slot 3 is set (3 flashes).
• Power off only when the yellow LED is lit following the desired slot setting.
• When you power on the active slot will correctly point to slot 1, 2 or 3.

OPTION 2: Remove and reprogram the EEPROM or config PIC externally. (Note: It is the PIC chip that actually holds the slot selection - you will only need to reprogram the PIC if you have old firmware that doesn't support the manual slot selection. If you do reprogram the PIC, use the latest firmware .hex file so that you wont have to do so again.) If you reprogram the EEPROM, use "default.bin" from the folder development_files/eeprom image as this also contains the bootcode for SLOT 0.

OPTION 3: JTAG config. If none of the first 3 slots contain OSCA:

• Power off and connect a Xilinx JTAG cable to the V6Z80P.
• Install jumpers J1 and J2.
• Load the most recent OSCA project into Xilinx webpack ISE and send the OSCA config .bit file from the PC to the V6Z80P via JTAG.
• If the bootcode is intact in the EEPROM, the system will start as normal allowing you to load EEPROM.EXE via FLOS. If the bootcode checksum fails the screen will flash magenta, then grey. See "bootcode problems" below.
• Remove jumpers J1 and J2 next time you power off so that the system automatically configures from the EEPROM.

V6Z80P+ BOARD

OPTION 1: Assuming there is a working config in Slot 1 - 7 and the problem is just that the Active Slot selection is pointing at a bad config:

• Power off.
• Install jumper J2 only
• Power on (yellow led flashes rapidly).
• Remove jumper J2
• The yellow LED will flash once, pause about 5 seconds, then flash twice, pause 5 seconds, then flash three times and so on - the number of flashes represents the slot selection. During the pause following the slot selection you require, replace the jumper - the LED will then stay on permanently signifying that the slot has been set.
• Power off and remove Jumper J2.

OPTION 2: JTAG configuration. (If none of the first seven slots contain OSCA)

• Power off and connect a Xilinx JTAG cable to the V6Z80P.
• Install jumpers J1 and J2.
• Load the most recent OSCA project into Xilinx webpack ISE and send the OSCA config .bit file from the PC to the V6Z80P via JTAG using Impact.
• If the bootcode is intact in the EEPROM, the system will start as normal allowing you to load EEPROM.EXE via FLOS. If the bootcode checksum fails the screen will flash magenta, then grey. See "bootcode problems" below.
• Remove jumpers J1 and J2 next time you power off so that the system automatically configures from the EEPROM.

Bootcode Problems

If the OSCA ROM cannot load a valid bootcode file from the EEPROM, the display will flash magenta (bad CRC) or green (time out). If OSCA version 661 or above is installed it is possible to send the bootcode file manually via the serial link when the display turns grey.

It is also possible to force serial transfer of the bootcode on power up by holding UP+RIGHT+FIRE on a joystick in port A. (Note: The transfer must be at 115200 BAUD).